1. Field of the Invention
The present invention relates to a voltage driven type MOS controlled thyristor and method for fabricating the same which has a four layer pnpn structure turned on and which off by two MOS gates, and is used as a power switching device.
2. Description of the Prior Art
Gate-turnoff thyristors (GTOS) that can be turned off by a gate signal are extensively employed. A GTO, however, has a disadvantage in that it requires a relatively large gate-driving power to turn off because it is a current driven device. To overcome this disadvantage, a voltage driven MOS gate transistor is proposed. An MOS gate transistor, like an insulated gate bipolar transistor (IGBT), has a structure to drive a wide base transistor by an MOS gate. An MOS gate thyristor, however, differs from an IGBT in that, although an IGBT does not latch the inner parasitic thyristor does, an MOS gate thyristor latch it so that not only the gate voltage but also the anode voltage must be reversed to turn-off the device.
MOS controlled thyristors (MCT) have been proposed which use voltage driven MOS gates to turn on and off the device. The MCT has a structure such that MOSFETS incorporated into the pnpn thyristor turn on and off the thyristor. More specifically, as shown in FIG. 1, on a low resistivity n+ layer (a first layer) 1, a low resistivity p+ layer (a second layer) 2 is formed, which is followed by a high resistivity p- layer (a third layer) 3. In the surface of the p- layer 3, an n layer (a fourth layer) 4 is selectively formed, and then, in the surface of the n layer 4, a p layer (a fifth layer) 5 is selectively formed. Subsequently, in the surface of the p layer 5, a p+ layer (a sixth layer) 6 and n+ layers (seventh layers) 7 are selectively formed. In addition, gate electrodes 9 are formed, via gate insulating films 8, on surface regions 15 of the n layer 4 between the p layer 5 and the p- layer 3, and on surface regions 17 of the p layer 5 between the n+ layer 7 and the n layer 4 so that the surface regions 15 and 17 form channel regions. Further, an anode electrode 10 making contact with the surface of both the p+ layer and the n+ layers 7, and a cathode electrode making contact with the n+ layer 1 are provided. The anode electrode 10 is insulated from the gate electrodes 9 with insulating layers 12.
This MCT is activated by applying a voltage to the gate electrodes 9 and the cathode electrode 11 with the anode electrode being grounded. To turn on the MCT,, a negative voltage is applied to the gate electrodes 9 so that p channels are formed in the surface regions 15 of the n layer 4 between the p layer 5 and the p- layer 3. Thus, holes flow through the p channels toward the cathode electrode 11 when a negative voltage is applied to the cathode electrode 11, thereby turning on the n+/p+ junction 19 between the n+ layer 1 and the p+ layer 2, and resulting in injection of electrons from the n+ layer 1 into the p+ layer 2. The electrons, passing through the p- layer 3 and the n layer 4, turn on the p/n junction 21 between the n layer 4 and the p layer 5 and the p/n junction 23 between the n layer 4 and the p+ layer 6. Thus, hole injection from the p layer 5 and p+ layer 6 to the n layer 4 takes place, thereby turning on the npnp thyristor. The on resistance of the thyristor is low owing to conductivity modulation taking place in the p+ layer 2, p- layer 3 and the n layer 4.
To turn off the MCT, a positive voltage is applied to the gate electrodes 9 so that n channels are formed in the surface regions 17 of p layer 5 between the n+ layer 7 and the n layer 4. Thus, the n+ layer 7 and the n layer 4 become equipotential, which in turn makes the p+ layer 6 and the n layer 4 equipotential because the p+ layer 6 is connected to the n+ layer 7 via the anode electrode 10. As a result, although electrons injected into the p+ layer 2 from the n+ layer 1 reach the p/n junction 21 between the n layer 4 and the p layer 5, and the junction 23 between the n layer 4 and the p+ layer 6, they flow into the anode electrode 10 through the n channels in the surface regions 17 so that hole injection from the p layer 5 into the n layer 4 does not occur, thus completing the turn off operation. Similar operations take place in a complementary MCT which has opposite conductivity type layers to those of the above MCT, has an MOS structure at the side of a cathode electrode when voltages of the opposite polarity are applied.
It is preferable that the MCT have a high turn-off speed as a switching device. To improve the turn-off speed, it is necessary to quickly remove excess carriers stored in the p+ layer 2, p- layer 3 and the n layer 4 in the conducting state. One method of improve the turn-off speed is to employ a cathode short structure in which the p+ layer 2 is short-circuited to the n+ layer 1 by the cathode electrode 11. This structure has an advantage that excess carriers stored in the p+ layer during the conducting state are easily removed. The structure, however, has a disadvantage that conductivity modulation suddenly takes place after a certain time has elapsed at the initial stage of turning-on owing to the reduction in the electron injection from the n+ layer 1 to the p+ layer 2, and hence, a negative resistance phenomenon is liable to occur during transition from the off to the on state, resulting in an increase in turn-on loss. On the other hand, in a normal cathode structure without a cathode short hole that short-circuits the p+ layer 2 to the cathode electrode 11, the negative resistance phenomenon is eliminated. This structure, however, reduces the carrier removal effect at the turn-off operation, and increases the turn-off loss.